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| STLC30R81 INTEGRATED RINGING SLIC FOR SHORT LOOP APPLICATIONS PRODUCT PREVIEW s s s s s s s s s s s s s s s MONOCHIP SLIC SUITABLE FOR SHORT LOOP APPLICATIONS 3.3V SUPPLY IMPLEMENTS ALL KEY FEATURES OF THE BORSHT FUNCTION DIFFERENTIAL OR SINGLE-ENDED Rx INPUTS INTEGRATED TRAPEZOIDAL WAVEFORM RINGING plus SINUSOIDAL and PWM WAVEFORM RINGING CAPABILITY TWO SELECTABLE PATH FOR SINUSOIDAL RING INJECTION SOFT BATTERY REVERSAL WITH PROGRAMMABLE TRANSITION TIME ON HOOK TRANSMISSION LOW POWER DISSIPATION IN ALL OPERATING MODES AUTOMATIC DUAL BATTERY OPERATION LOOP START, GROUND START FEATURES SURFACE MOUNT PACKAGE -40 TO +85C OPERATING RANGE TEST FUNCTION NO EXTERNAL COMPONENTS FOR POWER DISSIPATION TQFP44 (10 x 10) with slug ORDERING NUMBER: STLC30R81 functions (phone detection, loop-back, short circuit detection) are integrated in this device. It provides three ringing modes: Sinusoidal, Trapezoidal and PWM waveform. In sinusoidal ringing modes, depending on the CODEC's functionalities and characteristics Rxin+/Rxinor Rg+/Rg- paths can be selected. When CODEC can manage low frequency signals Rxin+/ Rxin- will be used. This device can also limit the peak current during OnHook/Off-Hook transition and Ring-trip detection. The device is based on BCD3S 90V technology and it can work at 3.3V power supply. The TQFP44 Package with SLUG increases the SLIC performance in terms of power dissipation making unnecessary the use of any external power components. DESCRIPTION The STLC30R81 is a low voltage SLIC suitable for short loop applications. All the BORSHT and test BLOCK DIAGRAM DET GDK/AL CRT LINE STATUS D0 D1 D2 D3 CS RES AC+ DC AC DC BGND LOGIC INTERFACE & DECODER ILT TIP SUPERVISION COMMANDS ILL LINE INTERFACE RING RLPBK RG+ RGRXin+ RXinZB TX AC PROCESSOR REFERENCE & BIAS SWITCHING + ILTF DC PROCESSOR RLIM RTH ZAC1 ZAC RS CAC IREF VCC VDD AGND CREV CSVR RD D01TL518 July 2003 This is preliminary information on a new product now in development. Details are subject to change without notice. 1/16 STLC30R81 PIN CONNECTION (Top view) GDK/AL RLPBK BGND CSVR RING DET N.C. N.C. N.C. N.C. 44 43 42 41 40 39 38 37 36 35 34 N.C. CS D0 D1 D2 D3 RES N.C. VDD VCC CRT 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 RS CREV VBAT1 VBAT2 RXin+ ZAC ZAC1 TX N.C. N.C. ZB D01TL512 TIP 33 32 31 30 29 28 27 26 25 24 23 IREF RLIM RTH N.C. AGND ILTF RD CAC RGRG+ RXin- PIN DESCRIPTION N 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 Pin N.C. CSI D0 DI D2 D3 RES N.C. VDD VCC CRT CREV N.C. VBAT1 N.C. VBAT2 TX ZB RS ZAC ZAC1 Rxin+ RxinIn Out In In In In In In In In In In In In In In In In In Type No Connection Chip-Select for input control bits; active low. Control Interface input bit 0. * Control Interface input bit 1. * Control Interface input bit 2. * Control Interface input bit 3. * Reset pin active low No Connection Control Interface Power Supply Positive Power Supply. GNDK detection capacitor Reverse polarity transition time programming capacitor No Connection Negative Battery Supply 1 (-38V Typ) No Connection Negative Battery Supply 2 (-74V Typ) 4 wires output stage (transmitting port) Canceling input of balance network for 2 to 4 wires conversion. Protection resistors image. It is connected between this node and ZAC AC impedance synthesis RX buffer output / AC impedance is connected between this node and ZAC 4 wires input stage (receiving port). A 100K external resistor must be connected to AGND to bias the input stage 4 wires input stage (receiving port). A 100K external resistor must be connected to AGND to bias the input stage. If not used must be tied to ground. Function 2/16 STLC30R81 PIN DESCRIPTION (continued) N 24 25 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 Pin RG+ RGCAC RD ILTF AGND N.C. RTH RLIM IREF N.C. CSVR N.C. BGND RING RLPBK N.C. TIP N.C. DET GDK/AL Out Out Out In Out In In In In In Type In In In In In In Function Sinusoidal ring signals input stage. A 100K external resistor must be connected to AGND to bias the input stage Sinusoidal ring signals input stage. A 100K external resistor must be connected to AGND to bias the input stage. If not used must be tied to ground. AC feed back input / AC-DC split capacitor is connected between this node and ILTF Ring trip threshold setting resistor Transversal Line Current Image Analog Ground No Connection Off-Hook threshold programming pin Limiting current programming pin Voltage reference output to generate internal reference current No Connection. Battery supply filter capacitor. No Connection Battery Ground B wire termination output. IB is the current sunk into this pin. External loop back resistor connects with this pin and tip No Connection. A wire termination output. IA is the current sourced from this pin. No Connection. Off-Hook and Ring-Trip detection bit active low Ground-key detection bit active low * Input pins provided with 15A sink to AGND pull-down ABSOLUTE MAXIMUM RATINGS Symbol VBAT VCC VDD A/R/BGND Battery voltage Positive supply voltage Control interface Supply Voltage AGND respect BGND Parameter Value -82 +VCC -0.4 to +7 -0.4 to +7 -2 to +2 Unit V V V V Note: 1. In case of power up, power failure or hot insertion with VBAT1, VCC present and VBAT2 floating the Absolute Maximum Rating can be exceeded. This effect can be prevented ensuring that VBAT2 is always present before VBAT1and VCC or connecting one schottky diode (e.g. BAT49X or equivalent between .VBAT1and VBAT2). OPERATING RANGE Symbol Topt VCC VDD VBAT1 VBAT2 A/BGND Positive supply voltage Control interface Supply Voltage Battery voltage Battery voltage AGND respect BGND Parameter Operating temperature range Value -40 to 85 3.3 to 3.6 3 to 5.5 -40 to -22 -74 to -65 -0.3 to +0.3 Unit C V V V V V 3/16 STLC30R81 THERMAL DATA Symbol Rth j-amb Rth j-amb Parameter Thermal resistance Junction to Ambient (2 layer board) Typ. Thermal resistance Junction to Ambient (1 layer board) Typ. Value 32 56 Unit C/W C/W OPERATING MODES It is possible to choose several operating modes just setting the proper Input D0, D1, D2, and D3. The table below (Tab.1) shows these modes: Table 1. Ctrl Interface Inputs D0 0 0 1 0 0 0 1 1 1 1 0 0 1 1 0 1 D1 0 0 1 0 1 1 0 0 1 1 1 1 0 0 0 1 D2 0 0 0 1 0 1 0 1 0 1 0 1 0 1 1 1 D3 0 1 1 0 0 0 0 0 0 0 1 1 1 1 1 1 Power down Power down Power down Stand-by Active normal polarity Active reverse polarity Trapezoidal ringing normal polarity Trapezoidal ringing reverse polarity Ground start High impedance feeding Active normal polarity (On-Hook transmission) Active reverse polarity (On-Hook transmission) Ringing In Sinusoidal (or PWM) wave Rxin+/- In Ringing In Sinusoidal (or PWM) wave Rg+/- In Test mode: phone detection Test mode: loop back Test mode: short circuit detection Operating Mode DET Disable Disable Disable Off-Hook Off-Hook Off-Hook Ringing trip Ringing trip Off-Hook Off-Hook Off-Hook Off-Hook Ringing trip Ringing trip Phone detect Off-Hook Phone short Output GDK/AL Disable Disable Disable Gnd-Key Gnd-Key Gnd-Key Gnd-Key Gnd-Key Gnd-Key Disable Gnd-Key Gnd-Key Gnd-Key Gnd-Key Disable Disable Disable 01101110 Power Down It's an idle state characterized by very low power consumption; any functionality is disabled. It can be set during out of service periods just to reduce the power consumption. It is worth remarking that two other conditions can set the SLIC in IDLE state but with some differences as reported in the table below. Table 2. Power down IDLE STATE Power down command Reset Thermal alarm DET Disable Disable Low GDK/AL Disable Disable Low Stand By Mode selected in On-Hook condition when high immunity to the common mode currents is needed to prevent false Off-Hook detection. To reduce the current consumption, AC feedback loop is disabled. Only DET and 4/16 STLC30R81 GDK/AL detectors are active. DC line loop current is limited at 15mA (not programmable). DC characteristic is shown in Fig.1. The line feeding voltage in On-Hook is typically 42V @ VBAT2 = -74V. Figure 1. Characteristic in StBy Mode I 15mA RFEED = 2RP D03TL590 42V V Active - NP (normal polarity) or RP (reverse polarity) Mode selected to allow voice signal transmission. When in ACTIVE mode VBAT1 is selected automatically and the voltage drop in on-hook condition is 7.8V. Concerning AC characteristic the STLC30R81 allows to set 2Wire termination impedance by means of external scaled impedance. In ACTIVE mode the SLIC can perform battery reversal in a soft way, with programmable transition time, without affecting the AC signal transmission. It is possible to program, by means of an external resistor RLIM, the value of the current limitation in a range of 20 to 45mA. During On/Off-Hook transition, the SLIC line drivers limit the transient current at Ilim +13mA. Figure 2. DC Characteristic in Active mode IL 20mA ~ 45mA RFEED = 2RP D03TL591 VBAT1 -7.8V VL Active - ON-Hook transmission This mode is selected to allow caller ID transmission in On-Hook line condition. The line feeding voltage in OnHook transmission is 42V @ VBAT2 = -74V. High Impedance feeding As in Stand-By, this mode is set in On-Hook condition, with further reduced power consumption. Higher power efficiency turns back to a lower immunity of the Off-Hook detector to line common mode currents. The DC feeding shows a constant current characteristic (Ilim = 18mA) followed by a resistive range with an equivalent series resistance Rfeed = 1600+ 2Rp (Fig.3). The line feeding voltage in On-Hook is 50V @ VBAT2 = -74 Thermal protection circuit is still active, preventing the junction temperature, in case of fault condition, to exceed 150C. In High Impedance Feeding most of the circuit is switched off, only the circuit, dedicated to Off-Hook detection, is powered. This allows reducing the total power consumption in On-hook to 30mW (typical). 5/16 STLC30R81 Figure 3. DC Characteristic in Hi-Z Feeding I 18mA RFEED = 1600+2RP D03TL592 50V V RINGING The STLC30R81 can provide three kind of signal waveform modes: Sinusoidal, trapezoidal, PWM. When this mode is selected, the SLIC is switched to VBAT2 (-74V); both DC/AC feedback loop are disabled and the SLIC line drivers operate as voltage buffers. Trapezoidal Ringing Waveform The ring waveform is obtained toggling the D2 control bit at the desired ring frequency. This bit in facts, controls the line polarity: 0 = direct, 1 = reverse. The transition between the two polarities is performed in a "soft" way. This means that TIP and RING wire exchange their polarities following a ramp transition (see Fig.4). The CREV is capacitor sets the shape of the ringing trapezoidal waveform. Once ring trip is detected, the DET output is set low and remains latched keeping the STLC30R81 in Stand-by mode until the operative mode is modified by any Input Word. Figure 4. Typical Ringing Waveform GND 3V typ TYP dV/dT set by CREV RING 3V typ VBAT2 D03TL593 CREV 22nF 27nF 33nF * Distortion already less than 10% Crest Factor @ 20Hz 1.2 1.25 1.33 Crest Factor @ 25Hz 1.26 1.32 Not significant (*) Sinusoidal Ringing Waveform The STLC30R81 has two couple of inputs: Rxin+/Rxin- and Rg+/Rg-; this means that it is possible to select two different paths to generate the sinusoidal waveform ringing. 6/16 STLC30R81 - Selecting Rxin+/Rxin- (first path), the sinusoidal waveform can be applied in differential mode (using both inputs) or single ended mode (connecting one of the two input pins directly to the GND). This signal comes from STLC5048 or other Codec - Selecting Rg+/Rg- (second path), the sinusoidal (or PWM) waveform ringing, can be applied in differential mode (using both inputs) or single ended mode (connecting one of the two input pins directly to the GND). The ring source (codec, waveform generators) can be always active and shared by multiple lines. Both DC/AC feedback loops are disabled except for the first path (Rxin+/Rxin-) that remains enabled. This functionality will be managed through an "Input Word" that allows the ringing signal, to flow through the line. The Table 3 shows how to select the proper input word. Table 3. Control Word Control Word D0 1 1 D1 0 0 D2 0 1 D3 1 1 Rxin+/ Rxin- Input selected Rg+/Rg- Input selected Input Selected Mode Figure 5. Ringing internal block D0 D1 D2 D3 DET Logic interface Ring Trip Rxin+ OpAmp 1 Ring Det + RxinRing Gain Internal switch - Rg+ OpAmp 2 Rg- In On-Hook condition, Tip and Ring are biased at -VBAT2/2; the input signal is typically amplified at 35dB. Ring trip detection is performed sensing the variation of the AC line impedance from High (On-Hook) to Low (Off-Hook). This particular ring trip method, allows to operate without DC offset superimposed on the ring signal and therefore, obtain the maximum possible load driving capability, from a given negative battery. After Ring/ Trip detection, DET pin is set Low and remains latched keeping the STLC30R81 in Stand-by mode until the operative mode is modified by Input Word. PWM Ringing Waveform A pulse-width modulated (PWM) signal may be used to provide the ringing input to Rg inputs. The signal is applied through a low-pass filter and AC-coupled into Rg+. This approach gives a sine wave output at tip and ringing circuit. 7/16 STLC30R81 Figure 6. PWM signal Input vs Sinusoidal Output Rxin+ RxinOpAmp 1 CODEC IN PWM Ring Rg+ LPF Rg- OpAmp 2 GROUND START This mode is selected when the SLIC is adopted in a system using the Ground Start feature. In this mode, the TIP termination is set in High Impedance ( 100K ) while the RING one is active and fixed at -33V @ Vbat1 (= -38V). In case RING termination is connected to GND the sinked current is limited to 35mA. When RING is connected to GND both Off-Hook and Ground-Key detectors are set low. TEST MODES This device can provide three kind of tests: 1. Phone Detection 2. Short circuit 3. Loop back Phone Detection This test feature checks whether a phone is connected to the line. Starting from Active Reverse Polarity status, just changing the D0 input bit, it is possible to perform the Phone Detection function. The MCU measures the time span of DET. Time longer then 4ms indicates that a phone is hooked up with the line, if no phone is connected, the time span is less than 2ms. Table 4. Phone detection - D0 variation Control Word Operating Mode D0 D1 D2 D3 0 1 1 1 1 1 0 0 Active - Reverse Polarity High Impedance Feeding - Normal Polarity 8/16 STLC30R81 Figure 7. Phone detection Diagram Active R.P. HiZ Phone DET T>4ms No Phone DET T<2ms Short Circuit DET signal pin changes its logical level depending on the presence (or not) of short circuit at the output of the Line Card (See Tab.5). Table 5. Short Circuit Detection Control Word D0 D1 D2 D3 DET Short Circuit 0 No Short Circuit 1 1 1 1 1 Loop back The test is aimed at cheking detection and feeding circuitry functionalities as described in fig. 8. The external resistor RLPCK is closed internally between TIP and RING and emulates the phone resistance. Starting from ACTIVE mode, when loop back mode is selected DET pin will change its level. If DET pin is low it means that detection and feeding circuits work properly. If DET remains high it means that a failure has been detected. Table 6. Loop Back Detection Control Word D0 D1 D2 D3 DET Good 0 Fail 1 0 0 1 1 Figure 8. loop back detection diagram Active Loop Back Active DET Protection Mode Suggested protection circuit is based on programmable Trisil (like LCP1511/12/21) and the surge current is limited by the resistors RPT2 and RPR2, which are PTC types, protecting the device against both lightning and power-cross. Thermal overload: the integrated thermal protection is activated when Tj reaches 150C typ.; the Slic is forced in Power-down mode, DET and AL are set Low. For external applications, two diodes 1N4148 are suggested (Pls. see application diagram). 9/16 STLC30R81 Figure 9. Logic interface Input Timing t1 t3 t2 Min t1 t2 t3 t4 t5 t6 100ns 100ns 500ns 100ns 100ns 500ns CS D0/D1/D2/D3 DET/GDK t4 t6 t5 EXTERNAL COMPONENTS Table 7. External Components Name RREF Function Internal current programming resistor Battery ripple rejection capacitance Power supply filter Battery supply filter Battery supply filter Ring Trip threshold setting resistor Ground Key capacitance AC/DC splitter Capacitance Protection resistor image 2 Wire AC impedance SLIC impedance balancing network Line impedance balancing network AC feedback compensation Capacitance Line series Resistor Line series Resistor Line series Resistor Line series Resistor Current limiting setting resistor Formula IREF = 0.6/RREF CSVR = 1/(2 /P 1.3M) Typ. Value 30.1K1% 100nF 10% 100V @ 1.22Hz 100nF20% 100nF20% 100V 100nF20% 100V 4.12K1% @IRTH =24mA 470nF20% 6V @25Hz 10F 20% 15V @/sp = 10Hz 2.5K1% 12.5K1% 15K1% 15K1% 220pF 20% @ /o = 250KHz 30 - 1/4W1% 20 30 - 1/4W1% 20 26K1% CSVR CVCC CVB1 CVB2 RD CRT CAC RS ZAC ZA ZB CCOMP RPT1 RPT2 RPR1 RPR2 RLIM RTH* CREV CH LCP15xx RLPCK D1 D2 D3 DS1 (**) RD=100/IRT(*); 2K 26.1K1% 47nF for 5.67V/ms 220pF 20% 500 1.5W 20% 1N4148 1N4148 1N4148 BAT 49X (*) IRTILIM+10mA. The line drivers have output current limitation correspond to ILIM during the Ringing mode. (**) Alternative to a controlled power up sequence 10/16 VCC(3.3V) 0.1F VDD(3.3V) VCC(3.3V) VCC 0.1F VCC 61 60 59 58 20 ZAC 28 18 CAC 26 19 RLPBK 39 RLPBK TIP RPT1 RPT2 TIP 22 23 17 41 ZB CAC RS RS ILTF 57 IO11 IO10 RD IO9 ZAC1 21 9 10 37 29 27 IO8 RD VDD BGND AGND VCC IO7 0.1F GND VDD VDD 9 VEE 0.1F VSS 8 SUB 41 DXA GRX=+6dB GTX=-12dB DRA VFRO0 100K 35 19 20 21 22 23 24 IO5 D3 6 IO4 D2 5 IO3 D1 4 IO2 D0 3 IO1 GDK/AL 44 IO0 43 DET VFXI0 CTX 100nF TX RXinCRX RXin+ 11 DXB 33 10 DRB 15 PCM INTERFACE FS 16 MCLK 14 13 STLC5048 plus STLC30R81: Application Diagram TSX 12 VBAT2 LCP 1512 RING RING RPR1 RPR2 M0 27 STLC5048 STLC30R81 38 VCC M1 54 25 INT RG- 3 24 VBAT1 14 RG+ D2 D3 CS TO OTHER SLICs CS0 CS 2 7 RES CS1 CS2 CS3 VFRO1 11 CRT RTH RTH CRT VFXI1 VFRO2 VFXI2 VFRO3 VFXI3 TO OTHER SLICs 31 RLIM RLIM CCLK 28 29 53 52 39 38 42 43 48 47 46 ITH 4 VB1 (-38V) VBAT2 16 DS1 (*) D1 VB2 (-74V) CSRV 35 32 IREF REF 33 12 CREV SERIAL CONTROL PORTS CO 7 CI 5 6 CAP CREV CSRV 40 CAP 0.1F 49 34 VBG ILIM TO OTHER SLICs D01TL516 Figure 10. STLC5048 / STLC30R81 Application Diagram. (Single Ended Configuration) STLC30R81 (*) ALTERNATIVE TO A CONTROLLED POWER UP SEQUENCE 11/16 STLC30R81 STLC30R81 plus external generic CODEC or Ringing Waveform Generator Figure 11. STLC30R81 plus Generic Ringing Source - Application Diagram VDD(3.3V) VCC(3.3V) 0.1F 0.1F VDD ZAC1 ZA ZAC ZB ZB CCOM CRX+ RXin+ 23 CRX100K RXin100K TX CTX 100nF 17 41 TIP RS ZAC RS 18 20 19 22 ILTF 21 9 VCC 10 37 BGND 29 AGND RD 27 RD CH GRX=+6dB GTX=-12dB 28 CAC 26 RLPBK 39 RLPBK RPT1 LCP 1512 RING RPR1 from external CODEC or Ringing Waveform Generator (*) VBAT1 DS1 (**) 100K 100K D2 D3 RPR2 RPT2 TIP VBAT2 CAC STLC30R81 38 25 RING Rg- DET GDK/AL D0 43 44 3 4 5 6 CONTROL WORD D1 D2 D3 24 Rg+ TO OTHER SLICs CS RES 2 7 11 31 RTH RTH RLIM RLIM 32 IREF REF 33 CREV CREV 12 14 16 35 VBAT2 CSRV D1 CRT CRT (*) Single ended mode: Rg-pin connected to GND. Differential mode (**) ALTERNATIVE TO A CONTROLLED POWER UP SEQUENCE CSRV D01TL515 ELECTRICAL CHARACTERISTICS The limits listed below are guaranteed with the specified test condition and in the 0 to 70C temperature range. Performance over -40 to +85C range are guaranteed by product characterization. (Test condition, unless otherwise specified: VCC and VDD = 3.3V, VBAT1=-38V, VBAT2=-74V, Tamb=25C) AC CHARACTERISTICS Symbol Parameter Test Condition Min. Typ. Max. Unit Zil Iil Long Impedance Long Current Capability AC Each Wire H.I feeding / wire (On-Hook) Standby Active per wire Ilim=current limited in active mode (see also Rlim) IT = transversal current(*) 5 13 Ilim+ 13-IT 60 40 300 to 3400Hz 22 40 mApk mApk mApk L/T T/L 2wRL Long. To Transv. Transv. To Long. 2W return loss With normal Rp value @ f = 1KHz dB dB dB 12/16 STLC30R81 AC CHARACTERISTICS (continued) Symbol Parameter Test Condition Min. Typ. Max. Unit THL OVI G24 G42 G24fq G42fq V2wp V4wp Thd Trans-hybrid loss 2W overload level Transmit gain abs Receive gains abs. Tx gain variation vs frequency Rx gain variation vs frequency Idle channel noise at line terminals Idle channel noise at TX port Total harm. Dist. 2w-4w, 4w-2w 1020Hz; 20Log |VRX/VTX | Active Mode at line terminals on Ref. impedance 0dBm 1020Hz 0dBm 1020Hz Rel. 1020Hz, 0dBm 300 to 3400Hz Psophometric, Active on-Hook Psophometric, Active On Hook 0dBm, 1KHz, I 1 = 20 to 45mA 30 3.2 -11.95 5.75 -0.1 -0.1 -82 -90 -12.11 5.90 -12.25 6.05 0.1 0.1 -78 -84 -50 dB dBm dB dB dB dB dBmp dBmp dB DC CHARACTERISTICS Symbol Parameter Test Condition Min. Typ. Max. Unit Vloih Vlo Vlo Ilims Ilimb Ilima VIREF ITIP IGS TXoff Line voltage Line voltage Line voltage Short circuit current Short circuit current Lim. current accuracy Band GAP reference Il = 0, H.I. feeding Il = 0, Stby Active On-Hook TX Rloop = 0, STby Rloop = 0, H.I.feeding Rel to progr. Val. 20 to 45mA Active NP, RP H.I. feeding Ground Start Ground Start Ring to GND Active Mode 48 40 28 50.1 42 29.5 15 18 52 44 31 18 22 10 V V V mA mA % V A -10 0.56 1100 25 -200 0.60 1600 35 0.64 2100 100 45 200 Rfeed H.I. Feeding resistance Tip leakage current Ring lead current TX output offset mA mV DETECTORS Symbol Parameter Test Condition Min. Typ. Max. Unit Idet Off-Hook current threshold Stby, Active Off-Hook current thershold Off/On Hook Hyst. Dialling distortion Ground Key current Ground Start detection threshold ILL=IB-IA Rintrip detection threshold Accuracy Rel. to progr. Val. 6 to 11mA Active, NP, RP Rel. to progr. val. 3 to 6mA H.I. feeding Stby Active Active TIP and RING to GND or Ring to GND Igst = 2 x Idet -10 -10 5 10% -1 -9.4 -5 -15 20% Idet +10 +20 8 30% +1 % % mA m ms mA Idet H.I. Hys Td ILL Igst IRTA +5 +15 % % 13/16 STLC30R81 DIGITAL INTERFACE Symbol Parameter Test Condition Min. Typ. Max. Unit Inputs: D0, D1, D2, D3, CSIN Vih Vil Iih Iil Voh Vol Input high voltage Input low voltage Input High current Input low current Input high voltage Input low voltage VDD = 3.3V VDD = 3.3V 2 0.8 30 10 V V A A Outputs: DET, GDK/AL Iol = 0.1mA; CS = low V DD = 3.3V 2 0.5 V V Note: All digital inputs are TTL compatible POWER SUPPLY REJECTION Symbol Parameter Test Condition Min. Typ. Max. Unit PSRRC PSRRB VCC to 2W port VBAT to 2W port Vripple = 0.1 Vrms 50 to 4KHz Vripple = 0.1 Vrms 50 to 4KHz 27 30 dB dB POWER CONSUMPTION Symbol Parameter Test Condition Min. Typ. Max. Unit ICC VCC H.I. feeding On-Hook (Open Line) Stby On-Hook Active On-Hook Power Down On-Hook Tx 1.0 3.5 6.0 1.0 6.0 100 200 5.0 100 3.0 0.5 2.5 0.5 0.5 300 mA mA mA mA mA A A IBAT1 VBAT1 supply current H.I. feeding On-Hook (Open Line) Stby On-Hook Active On-Hook Power Down On-Hook Tx mA A A IBAT2 VBAT2 supply current H.I. feeding On-Hook (Open Line) Stby On-Hook Active On-Hook Power Down mA mA mA A A IDD VDD supply current Any operating mode SINUSOIDAL RING Symbol Parameter Test Condition Min. Typ. Max. Unit Line Offset Gain No Signal From Rx and Rg input Both differential and Single Ended Vin 1Vpp / 1 REN -3 33 35 +3 37 V dB THD 3 5 % 14/16 STLC30R81 mm DIM. MIN. A A1 A2 b c D D1 D3 e E E1 E3 H L L1 S S1 K ccc 6.00 6.00 0.45 11.80 9.80 0.05 1.35 0.30 0.09 11.80 9.80 12.00 10.00 8.00 0.80 12.00 10.00 8.00 5.89 0.60 1.00 0.236 0.236 0 (min.), 3.5 (typ.), 7(max.) 0.10 0.004 0.75 0.018 12.20 10.20 0.464 0.386 1.40 0.37 TYP. MAX. 1.60 0.15 1.45 0.45 0.20 12.20 10.20 0.002 0.053 0.012 0.003 0.464 0.386 0.472 0.394 0.315 0.031 0.472 0.394 0.315 0.232 0.024 0.039 0.030 0.480 0.401 0.055 0.014 MIN. TYP. MAX. 0.063 0.006 0.057 0.018 0.008 0.480 0.401 inch OUTLINE AND MECHANICAL DATA TQFP44 (10x10x1.40mm) with Slug Down 0049510 D 15/16 STLC30R81 Information furnished is believed to be accurate and reliable. However, STMicroelectronics assumes no responsibility for the consequences of use of such information nor for any infringement of patents or other rights of third parties which may result from its use. No license is granted by implication or otherwise under any patent or patent rights of STMicroelectronics. Specifications mentioned in this publication are subject to change without notice. This publication supersedes and replaces all information previously supplied. STMicroelectronics products are not authorized for use as critical components in life support devices or systems without express written approval of STMicroelectronics. The ST logo is a registered trademark of STMicroelectronics (c) 2003 STMicroelectronics - All Rights Reserved STMicroelectronics GROUP OF COMPANIES Australia - Brazil - Canada - China - Finland - France - Germany - Hong Kong - India - Israel - Italy - Japan -Malaysia - Malta - Morocco Singapore - Spain - Sweden - Switzerland - United Kingdom - United States. http://www.st.com 16/16 |
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